• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    An automatic gain control arrangement is provided for an analog to digital (A/D) converter in a television signal processing system. A gain-controlled source of analog signals applies a video information signal to the input of an A/D converter. The A/D converter produces digitized video signal samples at an output which is coupled to a digital peak detector. The digital peak detector detects the level of the digital samples of the synchronizing signal components. The detected sync signal level is compared with a desired value or range of values. If the detected sync signal level is not at the desired level or is outside the desired range, the count of a counter is incremented or decremented accordingly. The count of the counter is converted to an analog voltage which is applied to the gain-controlled signal source to control the level of the analog signal applied to the A/D converter. The analog voltage may also be combined with a control voltage produced by an analog peak detector, which detects the level of the input signal to the A/D converter, to produce a composite gain control signal.
    公开号:SU1321384A3
    申请号:SU833558000
    申请日:1983-02-18
    公开日:1987-06-30
    发明作者:Алан Стеклер Стивен；Рюбен Балабан Альвин
    申请人:Рка Корпорейшн (Фирма)；
    IPC主号:
    专利说明:

    The invention relates to television technology and can be used in television receiving equipment.
    The purpose of the invention is to improve the accuracy of the automatic gain control.
    Figure 1 shows the structural electrical circuit of the proposed digital television receiver; figure 2 - the same digital amplitude detector.
    The digital television receiver (Fig. 1) contains a high frequency (RF) unit 1, an intermediate frequency signal filter 2, an intermediate frequency amplifier (IF amplifier) 3, an analog-to-digital converter (ADC) 4, a carrier frequency extraction unit 5, a frequency divider 6, phase detector (PD) 7, filter 8, automatic gain control (AGC) detector 9, adder 10, digital amplitude detector i1, video signal processing unit I2, digital analog conversion unit 13 (D / A), low-pass filters (LPF) 14 -1 red, 14-2 green and 14-3 blue signals on color, synchronization processor 15, a digital bandpass filter 16 .signala remaining audio signal detector 17 is accompanied by sound. Deni and LPF 18.
    B. Turn, the RF unit 1 contains the tuning voltage generator 19, the program selection unit (GDP) block 20, the adding circuit 21, the local oscillator 22, the mixer 23 and the high frequency amplifier 24 (UHF).
    Digital amplitude detector I 1 contains (FIG. 2) D-flip-flop 25, register 26, comparator 27, first element OR 285, two-threshold comparator 29, inverter 30, first element And 31, second element And 32, reversible counter 33, D / A converter 34 , the initial value register 35, the third element AND 36 and the second element OR 37,
    Digital television receiver works as follows
    The television signal received by the RF block 1 antenna is converted into an intermediate frequency signal, then generated by the intermediate frequency signal filter 2 and amplified by the IFC 3. From the IFC 3 output, the generated signal of the intermediate frequency of the normalized amplitude is fed to the first input
    A / D converter 4, which simultaneously performs the functions of a synchronous detector. The latter is ensured by the fact that the clocking of the ADC 4 according to its
    the second input is carried out with a frequency that satisfies the Kotelnikov theorem for vi, the zeosignal at the moments of the maxima of the intermediate frequency signal. Clock pulses for ADC 4
    are formed by the block 5 of the signal carrier signal and the frequency divider 6, and the synchronization of the clock pulses with the maxima of the intermediate frequency signal is performed by the circuit
    phase locked loop, including PD 7 and filter 8.
    The CPU supports a constant signal at the ADC 4 input and serves as a two-loop AGC system. The first loop includes the AGC signal detector 9 and the adder 10, and the second loop includes a digital amplitude detector 11 and the adder 10. The output signal from the adder 10 controls the gain
    UPC 3 at its second control input,
    i
    From the output of the ADC 4 video signal, in addition to the digital amplitude detector,
    is fed to the input of the video signal processing unit 12, which digitally separates the luminance and chrominance signals and processes them. Signals of the primary colors R, G and B in digital form come from the outputs of block 12 to the inputs of block 13 of the DAC, from the outputs of which the analog signals of the primary colors through the low-pass filter of red, green and blue colors 14-1, 14-2
    and 14-3 are output to further amplify and modulate the kinescope rays.
    The fourth output of the block 12 is connected to the input of the synchronization processor 15 and to the input of the digital audio band-pass filter 16, the output of which through the sound detector 17 and the low-pass filter 18 is output to further amplify and reproduce through speakers or telephones
    From one of the outputs of the signal synchronization processor 15 and with a frequency nf, a multiple of the horizontal frequency f, is fed to the second, the input of the FD 7, in which a control signal is produced, which comes in
    3132
    filter 8 to the control input of the RF block 1.
    In HF unit 1, the UHF 24 signal is compared with the signal of the local oscillator 22 with the signal of the GDP 20, as a result of which, at the output of the tuner 19, the coarse tuning voltage is formed, which after addition to the output filter filter 8 in the add 21. arrives at the control inputs of the local oscillator 22 and UHF 24, from which the signals arrive at the inputs of the mixer 23, which forms the intermediate frequency signal.
    The two-loop AGC system works as follows.
    The AGC signal detector 9 provides a control signal in accordance with the peak values of the intermediate frequency signal, maintaining a relatively constant signal level at the input of the A / D converter 4. The digital amplitude detector 11 generates a signal proportional to the peak values of the video signal during the passage of horizontal sync pulses (FID), and providing more accurate maintenance of the amplitude of the video signal in the digital television circuit
    receiver. I
    Digital amplitude detector 11 (figure 2) works as follows.
    In-line pulses are sent to the clock input of the D-flip-flop 25, which switches for a short time to the unit state and then is reset at the setup input to zero. Thus, at the direct output of D-flip-flop 25, a short positive pulse is formed, corresponding to a clock in the video signal (in the presence of synchronization). Digital video samples of positive polarity (down-sync) from ADC 4 are simultaneously received at the information input of register 26 and comparator 27. At the beginning of the FID, the register is pulse-transmitted from the D-flip-flop 25 received through the first element of the FID If, during the FID time, the value is smaller than that recorded in register 26, then it causes a pulse to form at the output of the comparator 27, which, through the first element OR 28, overwrites this value into register 26.
    44
    From the output of register 26, the measured value of the amplitude of the FID is fed to the input of a two-threshold comparator -29, which compares the value of the amplitude of the FID
    with fixed, predetermined values. When these values are exceeded, the corresponding outputs of the two-threshold comparator 29 generate signals permitting the passage of the horizontal pulses from the output of the inverter 30, and the elements 31 and 32, either summing or subtracting the inputs of the reversible counter 33.
    A reversible counter in accordance with the incoming signal increases or decreases by one the value of the code recorded in it, which through the DAC 34 enters the output of the digital amplitude detector 11 for
    gain control OAC 3. I
    To set the initial value of the code of the reversible counter 33, for example, at the time of power-up, a record of this code is used from the register 35 of the initial value on the installation signal generated at the time of power-up.
    In the event that the analog video signal goes beyond the dynamic range of the A / D converter 4, the signal from the overflow line of the output bus of the A / D converter 4 can reduce the code in the reversing counter 33 through the third element AND 36 and the second element OR 37.
    The proposed two-loop AGC system of a digital television receiver allows optimizing the dynamic characteristics of the AGC due to the coverage of the ADC 4. In addition, the analog and digital branches of the AGC system can monitor various components of the signal, which will also allow the ADC input signal to more accurately match its dynamic range.
    F o r mula inventions
    A digital television receiver containing a series-connected high-frequency unit, an intermediate frequency signal filter, an intermediate frequency amplifier (IF amplifier) and
    An automatic gain control signal detector (LRU), as well as an analog-to-digital converter (ADC /, the output of which is connected to the input of the video signal processing unit, the first
    five . 13
    three outputs of which are connected to the corresponding inputs of a digital-to-analog conversion unit (DAC), to the three outputs of which are connected the outputs of low-pass filters of the red, green and blue colors, the fourth output of the video processing unit is connected to the inputs of the synchronization processor and the digital band-pass sound signal filter a track whose output through an audio signal detector is connected to the input of a low-pass filter, the output of which is the sound signal output It is characterized by the fact that, in order to improve the accuracy of the automatic gain control, an adder, a digital amplitude detector, a frequency divider, as well as a carrier frequency signal extractor, a phase detector and a filter connected in series between the output of the AMF and the control input are introduced. the high-frequency unit, the second input of the phase detector is connected to the first output of the synchronization processor, the first input of the ADC is connected to the output of the IFA, the second input of the DAC is connected to the second output of the block through the frequency divider a carrier signal, the output through a digital amplitude detector is connected to the first input of the adder, the second input of which is connected to the output of the AGC signal detector, the output is connected to the control input of the amplifier, and the second input of the digital amplitude detector is connected to the second output of the synchronization processor. by this
    46
    digital amplitude detector content- | there is a register, the output of which is connected to the input of the two-threshold comparator and with the first input of the comparator, the second input of which is combined with the information input of the register and is the first input of the digital amplitude detector, the output of the comparator is connected to the control input of the register through the first OR element, the second input connected to the direct output of the D-flip-flop, the inverse output of which is connected to the input of the setup in the D-flip-flop, and the clock input is the second input of the digital amplitude detector and is connected via an inverter to the first in the first element And, in the second input of which is connected to the first input of the two-threshold comparator, and
    the output is connected to the summing input of the reversible counter, the information inputs of which are connected to the output of the register of the initial value, the record control input is the input
    the setup signal, the output is connected to the input of the DAC, the output of which is the output of the digital amplitude detector, and the input of the reversal counter is connected to the output of the second
    element AND, the first input of which is combined with the first input of the first element AND, and the second input is connected to the output of the second element OR, the first input of which is connected to the second output of the two-threshold comparator, and the second, input to the output of the third element And, the first and second inputs which are the inputs of the overflow signal and the horizontal sync pulses
    respectively.
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    Editor Y. Sereda
    Compiled by L. Stasenko
    Tehred V.Kadar Proofreader A.Zimokosov
    Order 2672/59, Circulation 638 Subscription
    VNIIPI USSR State Committee
    for inventions and discoveries 113035, Moscow, Zh-35, 4/5 Raushsk nab.
    Production and printing company, Uzhgorod, st. Project, 4
    权利要求:
    Claims (1)
    [1]
    Claim
    A digital television receiver containing a serially connected high-frequency unit, an intermediate-frequency signal filter, an intermediate-frequency amplifier (IFA) and an automatic gain control (AGC) signal detector, as well as an analog-to-digital converter (ADC output of which is connected to the input of the video signal processing unit, the first
    5 · i 31 the three outputs of which are connected to the corresponding inputs of the digital-to-analog conversion unit (DAC), the three · outputs of which are connected to the outputs of the low-pass filters, respectively. signals of red, green and blue colors, the fourth output of the video processing unit is connected to the inputs of the synchronization processor and a digital band-pass filter of the sound signal, the output of which through the detector of the sound signal is connected to the input of the low-pass filter, the output of which is the output of the sound signal, characterized in that, in order to improve the accuracy of automatic gain control, an adder, a digital amplitude detector, a frequency divider, as well as an output unit are introduced carrier signal, phase detector and filter, connected in series between the output of the frequency converter and the control input of the high-frequency unit, the second input of the phase detector is connected to the first output of the synchronization processor, the first input of the ADC is connected to the output of the frequency converter, the second input of the DAC through the frequency divider is connected to the second the output of the carrier signal signal isolation unit, the output through a digital amplitude detector is connected to the first input of the adder, the second input of which is connected to the output of the AGC signal detector, the output is connected to the control the input of the amplifier, and the second input of the digital amplitude detector is connected to the second output of the synchronization processor, while
    1384 6 digital amplitude detector contains | there is a register whose output is connected to the input of the two-threshold comparator and to the first input of the comparator, the second input of which is combined with the information input of the register and is the first input of the digital amplitude detector, the output of the comparator is connected to the control input of the register through the first OR element, the second input of which connected to the direct output of the D-flip-flop, the inverse output of which is with the installation input to О of the D-flip-flop, and the clock input is the second input of the digital amplitude detector and is connected through the inverter to the first the course of the first element And, the second input of which is connected to the first input of the two-threshold comparator, and the 20 output is connected to the summing input of the reverse counter, the information inputs of which are connected to the output of the initial value register, the recording control input is input 25 of the setup signal, the output is connected to the DAC input, the output of which is the output of a digital amplitude detector, and the subtraction input of the reverse counter is connected to the output of the second 30 element And, the first input of which is combined with the first input of the first element nta, and the second input is connected to the output of the second OR element, the first input of which is connected to the second output of the two-threshold comparator, and the second input is connected to the output of the third AND element, the first and second inputs of which are inputs of the overflow signal and horizontal sync pulses, respectively.
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    同族专利:
    公开号 | 公开日
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    PT76177B|1986-03-19|
    FI75963B|1988-04-29|
    BE895964A|1983-06-16|
    CA1195770A|1985-10-22|
    US4434439A|1984-02-28|
    FI830511A0|1983-02-15|
    AT386916B|1988-11-10|
    JPS58154982A|1983-09-14|
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    FI830511L|1983-08-23|
    FR2522233B1|1986-04-11|
    PT76177A|1983-03-01|
    DD207796A5|1984-03-14|
    AU567489B2|1987-11-26|
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    YU36683A|1986-04-30|
    AU1142583A|1983-09-01|
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    DK163398B|1992-02-24|
    GB2115629A|1983-09-07|
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    FR2522233A1|1983-08-26|
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    JPH0523108B2|1993-03-31|
    DE3305919C2|1992-09-03|
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    PL240705A1|1983-09-12|
    SE8300804L|1983-08-23|
    GB2115629B|1986-06-25|
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    ATA60183A|1988-03-15|
    ES519798A0|1984-05-16|
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    IT1168763B|1987-05-20|
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    引用文献:
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    法律状态:
    优先权:
    申请号 | 申请日 | 专利标题
    US06/350,580|US4434439A|1982-02-22|1982-02-22|Digital television AGC arrangement|
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